HIGHER-ORDER PCM MULTIPLEX SYSTEMS

Introduction

Higher-order PCM multiplex is developed out of several primary multiplex sources. Primary multiplex is typically DS1 in North America and E1 in Europe; some countries have standardized on E1, such as most of Hispanic America. Not only are E1 and DS1 incompatible, the higher-order multiplexes, as one might imagine, are also incompatible. First we introduce stuffing, describe some North American higher-level multiplex, and then discuss European multiplexes based on the E1 system.

Stuffing and Justification 

Stuffing (justification) is common to all higher-level multiplexers that we describe in the following. Consider the DS2 higher-level multiplex. It derives from an M12 multiplexer, taking inputs from four 24-channel channel banks. The clocks in these channel banks are free running. The transmission rate output of each channel bank is nominally 1,544,000 bps. However, there is a tolerance of ±50 ppm (±77 bps). Suppose all four DS1 inputs were operating on the high side of the tolerance or at 1,544,077 bps. The input to the M12 multiplexer is a buffer. It has a finite capacity. Unless bits are read out of the buffer faster than they are coming in, at some time the buffer will overflow. This is highly undesirable. Thus we have bit stuffing. 

    Stuffing in the output aggregate bit stream means adding extra bits. It allows us to read out of a buffer faster than we write into it.

In Ref. 1 the IEEE defines stuffing bits as “bits inserted into a frame to compensate for timing differences in constituent lower rate signals.” CCITT uses the term justification. Figure 6.12 illustrates the stuffing concept. 

North American Higher-Level Multiplex 

The North American digital hierarchy is illustrated in Figure 6.13. The higher-level multiplexers are type-coded in such a way that we know the DS levels (e.g., DS1, DS1C, 

Pulse stuffing synchronization.
 

 

The North American Digital Hierarchy

DS2, DS3, DS4) that are being combined. For instance, the M34 multiplexer takes four DS3 bit streams at its input to form the DS4 bit stream at its output. We describe the operation of the M12 multiplexer because it typifies the series. The formation of the second-level North American multiplex, DS2, from four DS1 inputs is shown in Figure 6.14. There are four inputs to the M12 multiplexer, each operating at the nominal 1.544 Mbps rate. The output bit rate is 6.312 Mbps. Now multiply 1.544 Mbps by 4 and get 6.176 Mbps. In other words, the output of the M12 multiplexer is operating 136 kbps faster than the aggregate of the four inputs. Some of these extra bits are overhead bits and the remainder are stuff bits. Figure 6.15 shows the makeup of the DS2 frame.

The M12 multiplex frame consists of 1176 bits. The frame is divided into four 294- bit subframes, as illustrated in Figure 6.15. There is a control bit word that is distributed throughout the frame and that begins with an M bit. Thus each subframe begins with an M bit. There are four M bits forming the series 011X, where the fourth bit (X), which may be a 1 or a 0, may be used as an alarm indicator bit. When transmitted as a 1, no alarm condition exists. When it is transmitted as a 0, an alarm is present. The 011 sequence for the first three M bits is used in the receiving circuits to identify the frame.

It is noted in Figure 6.15 that each subframe is made up of six 49-bit blocks. Each block starts with a control bit, which is followed by a 48-bit block of information. Of these 48 bits, 12 bits are taken from each of the four input DS1 signals. These are interleaved sequentially in the 48-bit block. The first bit in the third and sixth block is

The formation of the DS2 signal from four DS1 signals in an M12 multiplexer

designated an F bit. The F bits are a 0101 . . . sequence used to identify the location of the control bit sequence and the start of each block of information bits.

Euopean E1 Digital Hierarchy

The E1 hierarchy is identified in a similar manner as the DS1 hierarchy. E1 (30 voice channels) is the primary multiplex; E2 is the second level and is derived from four E1s. Thus E2 contains 120 equivalent digital voice channels. E3 is the third level and it is derived from four E2 inputs and contains 480 equivalent voice channels. E4 derives from four E3 formations and contains the equivalent of 1920 voice channels. International digital hierarchies are compared in Table 6.2. Table 6.3 provides the basic parameters for the formation of the E2 level in the European digital hierarchy. 

Makeup of a DS2 frame

CCITT Rec. G.745 (Ref. 6) recommends cyclic bit interleaving in the tributary (i.e., E1 inputs) numbering order and positive/ zero/ negative justification with two-command control.10 The justification control signal is distributed and the Cjin bits (n c 1, 2, 3; see Table 6.3) are used for justification control bits.  

Positive justification is indicated by the signal 111, transmitted in each of two consecutive frames. Negative justification is indicated by the signal 000, also transmitted in each of two consecutive frames. No-justification is indicated by the signal 111 in one frame and 000 in the next frame. Bits 5, 6, 7, and 8 in Set IV (Table 6.3) are used for negative justification of tributaries 1, 2, 3, and 4, respectively, and bits 9 to 12 for positive justification of the same tributaries. 

  Besides, when information from tributaries 1, 2, 3, and 4 is not transmitted, bits 5, 6, 7, and 8 in Set IV are available for transmitting information concerning the type of justification (positive or negative) in frames containing commands of positive justification and intermediate amount of jitter in frames containing commands of negative justification.11 The maximum amount of justification rate per tributary is shown in Table 6.3.